In industrial applications (e.g., automotive), a company may want to take an advanced reduction instruction set computer machine (i.e., ARM) core out of a mission mode (i.e., functional operations) and into a test mode, while maintaining the remaining ARM cores and a level 2 (L2) cache in the mission mode. Further, in many industrial applications (e.g., automotive), the electronic circuits need to be continuously tested in order to ensure reliability and prevent software and/or hardware faults that may cause system downtime. Thus, in these industrial applications, there is a need for memory to be concurrently tested while functional operations are performed.
In an example of the automotive industry, a 200 millisecond (msec) cycle is needed to perform on-chip testing. In this scenario, a functional operation is issued, which is then followed by a test operation of the logic block. In this scenario, as it is hard to provide large blocks of contiguous test time, slow performance can result because no further functional operations can be issued until after the testing is complete.